Highly integrated semiconductor circuits are increasingly important, particularly in producing battery-operated devices, such as cell phones, portable computers, such as laptops, notebook and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers, and the like, and these integrated circuits increasingly include on-board data storage. As is known in the art, such data storage may take the form of dynamic memory in which arrays of cells are provided, wherein each cell is a storage capacitor formed with an associated adjacent access transistor. Data stored in such memory cells is actually a charge stored on a small capacitor, and the data is accessed by a sense amplifier.
Sense amplifiers are differential amplifiers. The input and output lines are the same, typically referred to as bit lines or column lines, and the sense amplifier operates by first receiving a small differential voltage on one of the bit lines, while the other remains at a nominal pre-charged or equalized voltage. The small differential voltage is the result of one memory cell coupled on one of a pair of complementary bit lines being discharged (or, alternatively, charged) in response to a row selection line, or word line, being active. Typically the memory cell has a single access transistor with its gate or control terminal coupled to the row line. Some time after the row line becomes active and the small differential voltage appears on one of the complementary bit lines, the sense amplifier will sense the differential voltage and input it into a differential input latch circuit. This cross-coupled latch circuit will then amplify the small differential input voltage so that a full logic level differential voltage appears on the complementary bit lines. This mechanism thus allows an output circuit to couple the pair of bit lines to a data output circuit for the memory. The full logic level also allows the memory cell to restore the data into the memory cell storage capacitor. Because the access cycle (read) is a destructive read out cycle the cell charge must then be restored following the read in order for the cell to maintain its value.
Dynamic memory cells may be used in stand alone, or commodity, memory devices such as DRAM integrated circuits (ICs). These ICs are usually supplied in the form of cards populated with integrated circuits to make a complete array of memory, for example SIMM or DIMM cards, and sold as a finished memory for a desktop or laptop PC. Increasingly, embedded memory is becoming important in the production of advanced integrated circuits. These embedded memory modules may be a portion of an integrated circuit that provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These devices may provide, for example, all of the circuitry needed to implement a cell phone, or a personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like. The embedded memory arrays used in such devices must be very space efficient, power efficient, reliable and compatible with semiconductor processes that form logic circuitry and other types of circuitry on board the same device.
As integrated circuits are fabricated using semiconductor processes with smaller and smaller feature sizes, the tendency for devices to have device mismatch problems increases. Smaller MOS devices are subject to more short channel effects and higher leakage currents, which require higher threshold voltages Vt. Smaller geometries can lead to higher threshold voltages Vt mismatches between devices, as these mismatches scale inversely to the square root of the product of gate width times length. Transistors fabricated on the same integrated circuit may have widely varying threshold voltages Vt due to these device mismatches.
A differential circuit such as a sense amplifier has multiple devices operating in a balanced fashion and thus any device mismatches may lead to incorrect operation. A paper studying the effects of mismatches in sense amplifiers for DRAMs is “Mismatch Sensitivity of a Simultaneously Latched CMOS Sense Amplifier,” Sarpeshkar, et al., IEEE Journal of Solid State Circuits, Vol. 26, No. 10, October 1991, pp. 1413-1422. In the paper the ideal CMOS sense amplifier, such as in FIG. 1, is described as being perfectly balanced when the parameters of the four transistors that make up the two, cross-coupled inverters of the sense latch are all perfectly matched, that is the threshold voltages and the parasitic capacitances such as Cgp (for PMOS) and Cgn (for NMOS) and the line capacitances of the bit lines Cbl are all in balance. The ideal sense amplifier is also vertically matched when the word line W/L ratios of the PMOS and NMOS transistors are ratioed so that the pull up transistors (P types, usually with smaller gains) are balanced with the pull down transistors (N types, with larger gains). The paper also illustrates that if the sense amplifier is not perfectly matched, and the sensed voltage is small, the mismatch can cause errors in operation, the sense latch can take the wrong value.
The criterion for correct sense amplification sensing may be stated that the voltage being sensed, ΔVbl, must be greater than the mismatched voltages caused mostly by the NMOS Vt mismatches:ΔVbl=Cs/(Cs+Ct)*(Vsn−Vbl)*(1−exp(−αt0)).  (1)
The sensitivities of capacitances Cs, Ct and α to the differential voltage ΔVbl may be calculated and modeled as independent Gaussian random variables, where Cs, Vsn and α are the cell capacitance, cell storage voltage, and the inverse of the charge sharing time constant, that is α=gmc/(Cs∥Ct), where gmc is the gm of the cell pass transistor, and Ct is Cbl (bitline capacitance) plus the SA device loadings.
In the prior art, sensing errors in sense amplifier operations were often avoided by determining a minimum supply voltage level (Vcc), i.e., the minimum supply voltage level that can be used for reliable operations in the sense amplifier. As transistor mismatches increase for a particular process technology (mismatches increase with smaller minimum feature sizes), the Vcc minimum voltage that can reliably be used to supply the memory circuitry is increased. This increase in the required minimum Vcc results in increased power consumption and is undesirable. Also, the speed of the memory operations is hindered by the time needed for the bit lines to reach full Vdd levels with these higher Vcc specified. The major difficulties of advanced semiconductor process memory design are 1) higher voltage threshold Vt., 2) lower supply voltage; and 3) worse mismatch. These difficulties result in a higher Vcc minimum requirement than is desired.
Thus, there is a continuing need for a memory sense amplifier circuit that provides reliable and fast operation in spite of device mismatch problems that increasingly occur due to advances in semiconductor process technology, with a lower Vcc minimum requirement and error free operation, without significant increases in sense amplifier silicon area or power requirements.